The project developers LLVM released recently releasing the Heterogeneous Parallel Virtual Machine compiler (HPVM) 1.0, Which aims to simplify programming for heterogeneous systems and provides code generation tools for CPU, GPU, FPGA, and hardware accelerators domain specific (support for FGPA and accelerators was not included in version 1.0).
The main idea behind HPVM is to compile a unified representation of executable programs simultaneously that can be used to run on a variety of parallel hardware, including GPUs, vector instructions, multi-core processors, FPGAs, and various specialized accelerator chips.
Programming for heterogeneous parallel systems is complicated by the presence in a system of components (CPU cores, vector instructions, GPUs, etc.) that use different models to achieve parallelism, different instruction sets and different memory hierarchies, and each system has a combination of such components is changing.
The Illinois LLVM Compiler Research Group is pleased to announce the open source release of HPVM (version 1.0). HPVM is a reorientable compiler framework targeting CPUs, GPUs, and accelerators (this release does not include accelerator support) [1]. HPVM uses a target-independent compiler IR that extends the LLVM 9.0.0 compiler IR with an explicit hierarchical data flow representation that captures tasks, data, and pipeline parallelism.
This version is an important addition to our first version (version 0.5), which adds support for linear algebra tensor operations, Pytorch and Keras interfaces, approximations for convolution operators, and an efficient and flexible framework for approximation fitting.
It should be noted that the use of HPVM can achieve significant performance gains as eThe output performance of HPVM translators is comparable to that of OpenCL code handwritten for GPU and vector computing devices. Unlike other systems, HPVM attempted to combine three possibilities to organize heterogeneous computing: language- and hardware-independent intermediate representation, virtual instruction set architecture (V-ISA), and run-time programming.
The independent intermediate representation (IR) of the target system and the programming language used in HPVM is based on the intermediate representation of the LLVM 9.0 instructions and extends it with a hierarchical data flow graph to cover parallelism at the task, data, and computational pipelines level.
The HPVM intermediate also includes vector instructions and shared memory. The main goal of using intermediate representation is efficient code generation and optimization for heterogeneous systems.
Virtual Instruction Set Architecture (V-ISA) abstracts low-level hardware features and unifies various forms of parallelism and memory architectures using only the basic concurrency model, the data flow graph. V-ISA allows to achieve portability between different types of parallel computing equipment and allows not to lose performance when using different elements of heterogeneous systems. Virtual ISA can also be used to provide universal executable program code that can be run using CPU, GPU, FPGA, and various accelerators.
At the current stage of development, HPVM offers code generators capable of translating the application nodes defined by ISA Virtual to run using NVIDIA GPUs (cuDNN and OpenCL), Intel AVX vector instructions, and multi-core x86 CPUs. }
During execution, HPVM applies flexible scheduling policies for the computational process, implemented both on the basis of information about the program (graphical structure) and through the compilation of individual program nodes for execution on any of the computing devices of destination available in the system.
Compared to the first preview version, HPVM 1.0 includes support for linear algebra tensor operations, interfaces for Pytorch and Keras and an approximation tuning framework that automatically selects optimal approximations for certain tensor operations and selects a setting for optimal performance.
Finally, if you are interested in knowing more about this compiler, You can check the details in the following link.