AMD, Arm, ASE, Google Cloud, Intel Corporation, Meta, Microsoft, Qualcomm Incorporated, Samsung and TSMC announced the formation of an industry consortium that will establish standardized interconnection between different chiplets and foster an open chiplet ecosystem.
Universal Chiplet Interconnect Express (eICU) is a standard open interconnect of the industry that provides connectivity boxed high bandwidth, low latency, power efficient and profitable among chiplets.
This is planned to meet the projected growing demands for computing, memory, storage, and connectivity across continuous computing spanning cloud, edge, enterprise, 5G, automotive, high-performance computing, and wearables. UCIe is intended to provide the ability to package dies from a variety of sources, including different manufacturing labs, different designs, and different packaging technologies.
The consortium expect this standard, called Universal Chiplet Interconnect Express (UCIe), allow end users to “mix and match” components chiplet from multiple vendors to build a custom system-on-chip (SoC).
In general terms, there are two ways to build a system on chip modern (SoC). The monolithic integrated chips, the more traditional method, they combine all the elements of a semiconductor into a single piece of printed silicon. Conversely, chiplets take a different approach. Instead of creating one big chip with all the components, chiplets break things into components smaller ones that are then combined into a larger processor.
Therefore, the principle of chiplets is to combine and interconnect different modules, chiplets, which have their own matrix, within a single package. It's a "Lego" mode montage in a way.
The chiplet system has some advantages, since for example they can generate less waste (For example, if one core fails, it's easier to throw away one of the two 16-core chiplets than it is to waste an entire XNUMX-core monolithic chip.) The chiplet design also has advantages, as it allows companies to shrink critical components (such as CPU cores) to new, smaller processing nodes without having to shrink the entire SoC to make a match. Finally, chip combining allows companies to make larger chips than they could with a single monolithic design.
Ultimately, with a view to reducing costs and improving performance, a market for off-the-shelf modules (chiplets) is entirely possible. Just for such a practice to be viable, the interconnection between chiplets must be standardized, such as the different protocols used by a motherboard for example. That is what the UCIe wants to do.
Intel, AMD and others are already designing or selling chiplet-based processors One way or another: Most of AMD's Ryzen processors use chiplets, and Intel's upcoming Sapphire Rapids Xeon processors will too.
“AMD is proud to continue its long tradition of supporting industry standards that enable innovative solutions to meet the changing needs of our customers. We have been a leader in chiplet technology and welcome a multivendor chiplet ecosystem to enable customizable third-party integration,” said Mark Papermaster, executive vice president and chief technical officer, AMD. “The UCIe standard will be a key factor in stimulating system innovation by relying on heterogeneous calculation engines and accelerators that will allow obtaining the best optimized solutions in terms of performance, cost and energy efficiency. »
The UCIe project is still in its early stages. Currently, the standardization process is focused on establishing rules for interconnecting chips in larger packages. But there are plans to create a UCIe industry organization that will eventually help define next-generation UCIe technology, including "chiplet forms, management, enhanced security, and other essential protocols" in the future.
This means that one day there could be an entire ecosystem of chiplets that would allow companies to create a custom SoC by researching different components based on their needs, much like building a gaming PC.
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