QEMU 5.2 arrives with improvements for RISC-V, compiler change and more

QEMU

QEMU 5.2 has already been released and in this new version, in the preparation more than 3200 changes were made by 216 developers of which we can find live migration support for RISC-V, as well as experimental support for the RISC-V hypervisor, support for more boards and much more.

For those who are unfamiliar with QEMU, they should know that it is an emulator that allows you to run a program created for a hardware platform on a system with a completely different architectureFor example, running an ARM application on an x86 compatible PC.

In virtualization mode in QEMU, the performance of running code in an isolated environment is close to the hardware system due to direct execution of instructions on the CPU and the use of the Xen hypervisor or the KVM module.

Main novelties of QEMU 5.2

The compilation system has changed, compiling QEMU now requires the ninja toolkit to be installed.

Added support for the block device driver to use the process qemu-storage-daemon in the background as backend for vhost-user-blk, as well as a new QMP command 'block-export-add', which replaces the command 'nbd-server-add' and provides support for 'qemu-storage-daemon'.

For qcow2 images, support for extended L2 registers has been added, which allows the space to be allocated by incomplete groups (subclusters). To enable L2 when creating an image, you must specify the option "extended_l2 = on".

Also, the improved support for using qemu as an NBD client, as the number of situations that lead to waiting times when data is exchanged over the network was reduced, which causes guest blocking. Qemu-nbd provides the ability to specify multiple '-B name' options to specify multiple dirty bitmaps at once.

Another important change is the new high-performance migration mode with encrypted data transfer via TLS and multifd. The default migration bandwidth limit has been increased to 1 Gbps.

Migration parameter added 'block-bitmap-mapping', which allows more granular control over which bitmaps will be transferred during migration. The parameter works even if the host names differ from the source on the receiving end.

Also, new calls were added 'calc-dirty-rate' and 'query-dirty-rate' to predict the rate of updates during migration, taking into account the load associated with operations in RAM.

As well, we can find the support for the plates mp2-an386, mp2-an500, raspi3ap (Raspberry Pi 3 model A +), raspi0 (Raspberry Pi Zero), raspi1ap (Raspberry Pi A +) and npcm750-evb / quanta-gsj.

For the AArch32 architecture, support for the ARMv8.2 FEAT_FP16 (medium precision flaoting point) extensions is implemented.

Finally n are also mentionedNew options to virtiofsd to control rendering of xattr attribute names extended on the guest system, the separate connection of partitions with different mount points on the host system, and also to specify a sandbox isolation mechanism that is an alternative to pivot_root.

Y live migration support to RISC-V architecture emulator, as well as experimental hypervisor support for RISC-V updated to version 0.6.1. Added support for NUMA sockets on virt / Spike systems.

Of the other changes that stand out of this new version:

  • The guest-get-devices, guest-get-disks, and guest-ssh- {get, add-remove} -authorized-keys commands have been added to the QEMU guest agent (qemu-ga).
  • Added support for kvm-steal-time based accounting.
  • The HPPA architecture emulator supports booting NetBSD and very old Linux distributions, such as Debian 0.5 and 0.6.1.
  • The PowerPC architecture emulator has improved support for user-defined spacing for the NUMA topology.
  • The s390 architecture emulator for KVM added support for 0x318 diagnostic instructions.
  • The classic code generator TCG (Tiny Code Generator) implements support for additional z14 instructions.
  • On vfio-pci devices, information about the actual computer functionality is provided instead of the emulated features.
  • The Xtensa architecture emulator adds support for the DFPU coprocessor with single and double precision floating point opcodes.

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