Few days ago Chinese chipmaker T-Head (owned by Alibaba Group), released the results of the migration of the Android 10 platform to boards equipped with processors based on the RISC-V architecture.
An important feature of the new port is provide support for graphics and touchscreens, as well as working on real hardware. In parallel, the PLCT Lab project is also involved in Android porting for RISC-V, which in the fall of last year managed to load the minimal system environment in console mode using an emulator.
T-Head has ported Android 10 on the RISC-V architecture. The primary purpose of Android is to create an open software platform available to operators, OEMs and developers to bring their innovative ideas to life and present a successful real-world product that enhances the mobile experience for users. Video for Android on XuanTie910.
The operation of the new port is demonstrated on the ICE EVB board equipped with two processors XuanTie C910 1.2GHz (RISC-V 64), XuanTie C910V core for vector computing, and a GPU that supports hardware-accelerated decoding of HEVC, AVC, and JPEG formats.
T-Head C910 is an ultra-high performance 64-bit processor compatible with RISC-V yodelivers industry-leading performance in control flow, computation, and frequency through architecture and microarchitecture innovation. The C910 processor is based on the RV64GCV instruction set and has and implements TIE technology.
In the future, T-Head is expected to start producing RISC-V boards that can be used in multimedia devices, smart TVs, tablets and even smartphones.
For those unfamiliar with RISC-V, they should know that this provides an open and flexible machine instruction system that allows you to create microprocessors for arbitrary applications without requiring royalties or imposing conditions of use. RISC-V allows you to create completely open processors and SoCs.
Currently, on the basis of the RISC-V specification, several companies and communities under various free licenses (BSD, MIT, Apache 2.0) are developing several dozen variants of microprocessor cores, around a hundred SoCs and chips already produced. RISC-V support has been around since Glibc 2.27, binutils 2.30, gcc 7, and Linux kernel 4.15.
ICE EVB is a high performance SoC board based on XuanTie C910 developed by T-Head. The ICE SoC has integrated 3 XuanTie C910 (RISC-V 64) cores and 1 GPU core; with speed and intelligence with a high cost-benefit ratio. The chip can provide 4K @ 60 HEVC / AVC / JPEG decoding capability and varieties of high-speed interfaces and peripherals for data exchange and control; Suitable for 3D graphics, visual AI and multimedia processing.
As for the port, we can find that the patches are prepared for the Android Open Source Project code base (or better known as AOSP) and cover several subsystems, including the graphics stack, the bionic library, the dalvik virtual machine and frames.
For those who are interested in the port, you can find a script to create AOSP for RISC-V devices or run it in an emulator you can check the following link.
In addition, creation by BeagleBoard and Seeed also stands out of a new BeagleV board, built on a StarFive VIC7100 processor dual-core with RISC-V architecture.
The plate is specially developed for mass production of RISC-V computers filled with Linux-based software.
StarFive VIC7100 processor clocked at 1,5 GHz, includes MMU and other components required for full Linux distributions and supports vector extensions, includes NNE (Neural Network Engine) and NVDLA (Nvidia Deep Learning Accelerator) engines to accelerate learning systems Automatic, DSP Tensilica VP6 for Accelerate computer vision processing and hardware H264, H265, JPEG (4K @ 60FPS) encoders / decoders.
The board is equipped with 8 GB of RAM, WiFi, Bluetooth, 4 USB 3.0 ports, USB-C, Gigabit Ethernet, HDMI 1.4, TF card slot, two MIPI-CSI (Serial Camera Interface) slots and one MIPI-DSI 40-pin GPIO.
FreeRTOS, Debian, and Fedora are advertised as supported software. Production is scheduled to start in April and the plate will sell for $ 150.