Yadda ake aiki da vhdl ta amfani da software kyauta

Azuzuwan injiniyan lantarki yawanci ana karantawa ta amfani shahararrun kayan aiki, don haka koyaushe nakan dauki hoursan awanni ina neman in yi aikina software kyauta. Saboda wannan dalili, Na yanke shawarar raba abubuwan masu zuwa jagora.

Shigar da zama dole

Don tattarawa da kwaikwayon shirye-shiryenmu zamuyi amfani da GHDL, mai tattara kyauta bisa GCC. Don ganin sakamakon kwaikwaiyo, zamuyi amfani da GTKWAVE. A matsayina na edita na ba da shawarar Geany kamar yadda ya fahimci kusan dukkanin yarukan shirye-shirye.

sudo dace-samu shigar ghdl gtkwave geany

Misali aikin

Bari muyi amfani da wannan kwatancen a matsayin misali:

Kafin ƙirƙirar aiki, bari mu fara da ƙirƙirar babban fayil inda duk fayilolin za su karɓi bakuncin. A wannan yanayin, / gida / mai amfani / vhdl. A can za mu adana lambar tushe na shirye-shiryenmu tare da fadada .vhd.

Sannan zamu rubuta shirinmu ta hanyar amfani da Geany, kamar yadda aka gani a cikin sikirin.

Muna adana shi azaman kwatantawa.vhd.

Yanzu zamu buƙaci ƙirƙirar sigina don kwaikwaiyo. Don yin wannan, zamu ƙirƙiri wani ɓangaren da ke amfani da toshe na baya kuma zamu ƙayyade alamun.

Lines A <= "0011" bayan 0 ns, "0111" bayan 5 ns, "0111" bayan 10 ns; su ne waɗanda ke daidaita siginonin shigarwa a cikin lokaci

Muna adana fayiloli a cikin / gida / mai amfani / vhdl. Bayan haka, zamu buɗe tashar kuma tara:

ghdl -a kwatanta.vhd

Idan babu saƙonnin kuskure, tattarawar ya yi nasara.

Yanzu mun tattara "bangaren"

ghdl -a kwatanta_tb.vhd

Idan babu kuskure, zamu ƙirƙiri wanda za'a iya aiwatarwa:

ghdl -e kwatanta_tb

Aƙarshe, ya rage don yin kwaikwaiyo da adana sakamako a cikin mai suna "kwatanta.vcd"

ghdl -r kwatanta_tb --vcd = kwatanta.vcd

Domin ganin sakamakon zamuyi amfani da gtkwave:

Gtkwave kwatanta.vcd

Da zarar an buɗe, yi amfani da maɓallin Ctrl da linzamin kwamfuta don nuna alamun da suke sha'awar mu kuma latsa sa. Sannan danna sau biyu akan vectors din don ganin sakonnin daban. Bayan haka, danna dama a sigina don zaɓar tsari (binary, hex, octal, decimal, da sauransu)

Idan ya cancanta, maɓallin ƙara girman gilashi tare da murabba'i a tsakiyar yana daidaita zane zuwa allon.

ALU: bangaren lissafi da dabaru

Yayi, yanzu bari muyi wani abin da yafi birgewa: ALU (sashen fasaha da dabaru). Zai zama yanki mai ma'ana, ƙungiyar lissafi da mahara mai yawa.

Kwarewar hankali (LoU.vhdl)

     Laburare ieee; AMFANI DA IEEE.STD_LOGIC_1164.duk; AMFANI DA IEEE.NUMERIC_STD.duk;

ENTITY lou NE
PORT (op1: A cikin std_logic_vector (7 KASHE 0);
op2: A cikin std_logic_vector (7 KASHE 0);
aiwatar: IN std_logic_vector (3 KASHE 0);
Sake: OUT std_logic_vector (7 KASHE 0));
KARSHE lou;

ARCHITECTURE synth2 NA lou NE
SIGNAL a, b: BABU SA hannun (op1'range);
SIGNAL c: UNSIGNED (sake canzawa);
GAME
Tsari (a, b, aiwatarwa)
GAME
CASE tsari NE
LOKACIN "0000" => c <= SAMUN ((ba a), tsayinsa);
LOKACIN "0001" => c <= SAMUN ((a da b), tsayin tsayi);
LOKACIN "0010" => c <= SAMUN ((a ko b), tsayin tsayi);

LOKACIN "0011" => c <= SAMUN ((a xor b), tsawan tsayi);
LOKACIN "0100" => c <= SAMUN ((a nand b), tsayin tsayi);
LOKACIN "0101" => c <= SAMUN ((a ba b), tsayin tsayi);
LOKACIN SAURAN => banza;
KARSHEN LAMARI;
KARSHEN SHARI'A;

a <= BATSA (op1);
b <= BATSA (op2);
res <= std_logic_vector (c);

KARSHE synth2;

Ithungiyar lissafi (ArU.vhd)

     Laburare ieee; AMFANI DA IEEE.STD_LOGIC_1164.duk; AMFANI DA IEEE.NUMERIC_STD.duk;

ENTITY aru NE
PORT (op1: A cikin std_logic_vector (7 KASHE 0);
op2: A cikin std_logic_vector (7 KASHE 0);
aiwatar: IN std_logic_vector (3 KASHE 0);
Sake: OUT std_logic_vector (7 KASHE 0));
KARSHE aru;

ARCHITECTURE synth NA aru NE
SIGNAL a, b: BABU SA hannun (op1'range);
SIGNAL c: UNSIGNED (sake canzawa);
GAME
Tsari (a, b, aiwatarwa)
GAME
CASE tsari NE
LOKACIN "0000" => c <= SAMUN ((a + b), tsayinsa);
LOKACIN "0001" => c <= SAMUN ((a - b), tsayin tsayi);
LOKACIN "0010" => c <= SAMUN ((a * b), tsawan tsayi);

LOKACIN "0011" => c <= SAMUN ((a / b), tsawan tsayi);
LOKACIN "0100" => c <= SAMUN ((a + "1"), tsayinsa);
LOKACIN "0101" => c <= SAMUN ((b + "1"), tsayinsa);
LOKACIN SAURAN => banza;
KARSHEN LAMARI;
KARSHEN SHARI'A;

a <= BATSA (op1);
b <= BATSA (op2);
res <= std_logic_vector (c);

KARSHEN synth;

Plearamar (muxVector.vhd)

     Laburare ieee; AMFANI DA IEEE.STD_LOGIC_1164.duk; AMFANI DA IEEE.NUMERIC_STD.duk;

ENTITY muxVector NE
PORT (daga ARU: IN std_logic_vector (7 KASHE 0);
dagaLOU: IN std_logic_vector (7 KASHE 0);
sauyawa: IN std_logic;
fitarwa: daga std_logic_vector (7 DOWNTO 0));
KARSHEN muxVector;

GASKIYA canzawa na muxVector NE
GAME
tare da sauya zabi
fitarwa <= daga ARU lokacin '0', daga LOU lokacin da wasu;
KARSHEN canji;

ALU Bangaren (aluComponent.vhd)

     Laburare ieee; AMFANI DA IEEE.STD_LOGIC_1164.duk; AMFANI DA IEEE.NUMERIC_STD.duk;

ENTITY alu Bangaren NE
KARSHEN aluComponent;

ARCHITECTURE abubuwan shigarwa_aluWanda yake na aluComponent NE

KYAUTA aru
PORT (op1: A cikin std_logic_vector (7 KASHE 0);
op2: A cikin std_logic_vector (7 KASHE 0);
aiwatar: IN std_logic_vector (3 KASHE 0);
Sake: OUT std_logic_vector (7 KASHE 0));
KARSHEN HALATTA;

KYAUTA lou
PORT (op1: A cikin std_logic_vector (7 KASHE 0);
op2: A cikin std_logic_vector (7 KASHE 0);
aiwatar: IN std_logic_vector (3 KASHE 0);
Sake: OUT std_logic_vector (7 KASHE 0));
KARSHEN HALATTA;

MUHIMMAN MUXVector
PORT (daga ARU: IN std_logic_vector (7 KASHE 0);
dagaLOU: IN std_logic_vector (7 KASHE 0);
sauyawa: IN std_logic;
fitarwa: daga std_logic_vector (7 DOWNTO 0));
KARSHEN HALATTA;

SIGNAL outputARU: std_logic_vector (7 KASHE 0);
SIGNAL outputLOU: std_logic_vector (7 KASHE 0);
sigina Canja: std_logic;
siginar tsari: std_logic_vector (3 KASHE 0);
fitowar sigina: std_logic_vector (7 DOWNTO 0);
SIGNAL A: std_logic_vector (7 KASHE 0);
SIGNAL B: std_logic_vector (7 KASHE 0);

GAME
u0: aru MAP tashar jirgin ruwa (A, B, tsari, ARU fita);
u1: lou PORT MAP (A, B, tsari, LOU fitarwa);
u2: muxVector PORT MAP (outputARU, outputLOU, sauyawa, fitarwa);

A <= "00000011" bayan 0 ns, "00000111" bayan 5 ns, "00000111" bayan 10 ns, "00001001" bayan 15 ns, "00000000" bayan 20 ns, "00000101" bayan 25 ns, "00001111" bayan 30 ns, "00000101" bayan 35 ns;
B <= "00000010" bayan 0 ns, "00000100" bayan 5 ns, "00000010" bayan 10 ns, "00000011" bayan 15 ns, "00000100" bayan 20 ns, "00000110" bayan ns 25, "00001111" bayan 30 ns, "00000011" bayan 35 ns;
sauya <= '1' bayan 0 ns, '0 ′ bayan 5 ns,' 1 ′ bayan 10 ns, '0' bayan 15 ns, '1 ′ bayan 20 ns,' 0 ′ bayan 25 ns, '1 ′ bayan 30 ns, '0 ′ bayan 35 ns,' 1 ′ bayan 40 ns;
aiwatar <= "0000" bayan 0 ns, "0001" bayan 5 ns, "0010" bayan 10 ns, "0011" bayan 15 ns, "0100" bayan 20 ns, "0101" bayan 25 ns, "0110" bayan 30 ns;
Kayayyakin Kayayyakin Kare KARSHE;

Don kada mu ɓata lokaci wajen tattara umarni da umarni yayin aiki a kan shirin, muna adana fayil ɗin da ake kira compilar.sh tare da abubuwan da ke gaba a cikin babban fayil ɗin:

ghdl -a lou.vhd && ghdl -a aru.vhd && ghdl -a muxVector.vhd && ghdl -a aluComponente.vhd && ghdl -e aluComponent && ghdl -r aluComponent --vcd = alu & ghdlwave

Bude m, shigar da babban fayil kuma gudanar da rubutun:

cd / gida / mai amfani / vhdl sh tara.sh

Idan babu kuskure gtkwave zai buɗe kuma zamu iya ganin sigina:

Waɗannan kayan aikin sun kasance da amfani sosai kuma sun fi sauƙi amfani da su fiye da kayan aikin mallaka da muke amfani da su a cikin aji, wanda zato yake ɗaukar dogon lokaci don tattarawa. Tare da ghdl yana ɗaukar tsawon lokaci don sauya windows fiye da tattarawa.

Infoarin bayani game da VHDL

Ga wadanda sababbi zuwa vhdl, a nan suna da misali na asali na mai musu.

Misalin bidiyo:
http://www.youtube.com/watch?v=feVMXsyLSOU

Ka tuna cewa sabon juzu'in Ubuntu bashi da GHDL a wuraren adana su. Ana iya sauke wannan don Linux / Windows daga shafin aikin:
http://ghdl.free.fr/site/pmwiki.php?n=Main.Download