Google wants RISC-V to be seen as a "tier 1 platform" on Android
At the RISC-V Summit, Google announced its intention to officially support the RISC-V architecture on the Android platform.
It must be remembered that during the last quarter of 2022, the repository AOSP (Android Open Source Project), which develops the source code for the Android platform, began including changes that provide support for devices with processors based on the architecture RISC-V.
For those who are still unaware of RISC-V, you should know that it provides an open and flexible machine instruction system that allows microprocessors to be built for arbitrary applications without requiring fees or imposing conditions of use. RISC-V allows the creation of completely open SoCs and processors.
Currently, on the basis of the RISC-V specification, several companies and communities under various free licenses (BSD, MIT, Apache 2.0) are developing several dozen variants of microprocessor cores, about a hundred ready-made SoCs and chips. RISC-V support has been around since the releases of Glibc 2.27, binutils 2.30, gcc 7, and Linux kernel 4.15.
The changes are mainly prepared by Alibaba Cloud, but they are being promoted in collaboration with Google and through a dedicated Android SIG created by RISC-V International and open to other companies interested in running the Android software stack on RISC-V processors to join.
It is worth mentioning that Android, the operating system developed by Google, currently supports several different Instruction Set Architectures (ISAs), such as Arm and x86. Most devices that use Android, including smartphones, tablets, TVs, and smartwatches, use Arm-based chipsets.
What is an ISA architecture?
Understanding what the instruction set can do and how the compiler uses those instructions can help developers write more efficient code. It can also help them understand the compiler output, which can be useful for debugging. Arm opens up its instruction set architecture for Cortex M cores.
By allowing licensees to create their own custom instructions, lDevelopers can accelerate specialized workloads. The Arm ISA allows developers to write software and firmware that conform to Arm specifications, knowing that any Arm-based processor will run them just the same.
An instruction set architecture (ISA) is part of a computer's abstract model that defines how software controls the CPU. ISA acts as an interface between hardware and software, specifying what the processor can do and how it does it.
ISA is the only means by which a user can interact with the hardware. It can be considered the programmer's manual because it is the part of the machine that is visible to the assembly language programmer, compiler writer, and application programmer.
ISA defines the supported data types, registers, the way the hardware manages main memory, key features (such as virtual memory), the instructions a microprocessor can execute, and the input/output model of various ISA implementations, plus it can be extended adding instructions or other capabilities, or supporting addresses and larger data values.
The changes cover subsystems like the graphics stack, sound system, video playback components, bionic library, dalvik virtual machine, frameworks, Wi-Fi and Bluetooth stacks, RunTime, emulator, developer toolkit, and various third-party modules , including machine learning modules for text recognition, sound classification, and images.
Be supposed to to prepare a full version of Android optimized for RISC-V and moving from the prototype stage to the final product, there is still a lot of work to be done, which it can take several years. At the same time, for enthusiasts ready for experiments, a build system has already been released which allows you to evaluate the status of the Android branch "riscv64". Emulator support is expected in early 2023 and Android RunTime (ART) support for RISC-V is expected in Q2023 XNUMX.
Source: https://arstechnica.com